1. Technical Field
Embodiments of the invention relate to power semiconductor modules and, in particular, to power semiconductor modules wherein it is possible to reduce switching noise.
2. Related Art
FIGS. 7A and 7B are configuration diagrams of a heretofore known power semiconductor module 201, wherein FIG. 7A is a main portion plan view, and FIG. 7B is a main portion sectional view taken along the line A-A of FIG. 7A.
The power semiconductor module 201, being a power semiconductor module of a type wherein main electrodes of power semiconductor chips 205 are electrically connected by a plurality of post electrodes 211, is described in Japanese Patent Application Publication No. JP-A-2009-64852.
The power semiconductor module 201 of FIGS. 7A and 7B has an integrated structure in which an insulating substrate 202 and an implanted printed substrate 203 (hereafter the printed substrate) opposed to the insulating substrate 202 are sealed with an underfill material, a resin material 204, or the like, wherein a plurality of the power semiconductor chips 205 are mounted on the insulating substrate 202.
Furthermore, the power semiconductor module 201, by being packaged using an unshown resin case, functions as, for example, a general-purpose IGBT (insulated gate bipolar transistor) module. The insulating substrate 202 includes an insulating plate 206, a metal foil 207 formed on the bottom of the insulating plate 206 by a DCB (direct copper bonding) method, and a plurality of metal foils 208 formed on the top of the insulating plate 206 likewise by the DCB method.
Furthermore, the power semiconductor chip 205 is joined to the top of each metal foil 208 across a lead-free solder layer 209 of a tin (Sn)-silver (Ag) series. Also, a plurality of through holes 210 are provided in the printed substrate 203, an unshown thin-walled cylindrical plated layer is provided in each through hole 210, and the cylindrical post electrodes 211 are implanted one each in the through holes 210 across the respective cylindrical plated layers.
Also, the power semiconductor chips 205 are joined one each to the post electrodes 211 across respective solder layers 212. Also, the printed substrate 203 has a multilayer structure in which, for example, a resin layer 213 is disposed in the center portion, and a metal foil 214 is selectively formed by patterning on each of the top and bottom of the resin layer 213.
FIG. 8 is a circuit configuration diagram of a power conversion device using a power semiconductor module. The power conversion device is described in Japanese Patent Application Publication No. JP-A-2002-204580.
The power conversion device is divided broadly into three circuit sections as a circuit configuration, a noise filter section 215, a main circuit section 216, and a control circuit section 217. The noise filter section 215 is formed of a three-phase AC power source 218, reactors 219 connected in series one to each of three power lines via input terminals R, S, and T, ground capacitors 220, and interphase capacitors 221.
The noise filter section 215 has the function of filtering switching noise generated along with a switching operation of power semiconductor chips configuring a power converter such as an inverter. The main circuit section 216 is formed of a rectifier circuit 224 connected to the noise filter section 215, a smoothing capacitor 225 connected to a pair of output terminals of the rectifier circuit 224, and an inverter circuit 223 connected to the smoothing capacitor 225.
The inverter circuit 223 (configured of a power semiconductor module) has, for example, a switching element formed of an IGBT (insulated gate bipolar transistor) and a power semiconductor element 226 configured of a free wheeling diode, and each element is on/off controlled. Electric equipment, herein, a three-phase induction motor 227, is connected as a load of the inverter circuit 223. The control circuit section 217 is formed of a DC-DC converter 228 and a control circuit 229 including a CPU, ROM, RAM, and the like, which carry out various kinds of signal processing and control. The DC-DC converter 228 is connected to output terminals of the rectifier circuit 224, and the three-phase AC power source 218 is input into the DC-DC converter 228. Power converted to a predetermined value by the DC-DC converter 228 is supplied to the control circuit 229. The control circuit 229 is connected to a gate terminal of the switching element (power semiconductor element 226) of the inverter circuit 223. The switching element is on/off controlled based on a control signal from the control circuit 229, output voltage pulse-wave modulated (PWMed) thereby is output from output terminals U, V, and W, and the three-phase induction motor 227 rotates.
Also, it is described in Japanese Patent Application Publication No. JP-A-2011-147212 that, in only an upper arm wherein two semiconductor elements are connected in parallel, as a current imbalance occurs due to the semiconductor elements differing in inductance depending on a wire length, a configuration is adopted such that it is possible, even when a current imbalance occurs due to a difference in wire length, to suppress an imbalance in turn-off loss between the semiconductor elements, and thus reduce the loss, by making the capacitance of a snubber capacitor with a shorter wire length higher than the capacitance of a snubber capacitor (Cs2) with a longer wire length.
However, with the heretofore known power semiconductor module 201, there have been the following problems. The first problem is a problem of switching noise. A switching operation of a switching element such as an IGBT configuring the power semiconductor module 201 is carried out based on a pulse-wave modulated (PWMed) drive signal with a carrier frequency of in the order of several kHz to a dozen kHz.
Switching noise with a frequency component of tens or more of kHz is generated in the switching element (IGBT or the like) by the switching operation, adversely affecting an external device. In order to suppress the adverse effect, the noise filter 215 is installed in the power conversion device, as shown in FIG. 8. However, as the noise filter 215 is installed outside the package of the power semiconductor module 201 so as to be distanced from the switching element (IGBT or the like) configuring the power semiconductor module 201, it is difficult to sufficiently suppress switching noise.
The second problem is a thermal problem. The power semiconductor chips 205 are being reduced in size and thickness year by year in order to reduce the cost of the power semiconductor module 201, because of which a rise in temperature of the power semiconductor chips 205 due to an increase in current density has become a problem.
The package size of the power semiconductor module 201 is also being reduced in size along with the reduction in size of the power semiconductor chips 205, and thermal resistance Rjc from the power semiconductor chips 205 to a cooling body increases. Also, a rise in temperature of the power semiconductor chips 205 from the effect of a thermal interference between adjacent power semiconductor chips 205, or the like, remains as a problem.
Also, in Japanese Patent Application Publication No. JP-A-2011-147212, it is described that it is possible to suppress an imbalance in turn-off loss between the semiconductor elements, and thus reduce the loss, even when a current imbalance occurs due to the difference in wire length, but no measure to suppress switching noise generated in the switching element is described. Thus, as described above, there are several shortcomings in the related art.